Advanced semiconductor chips employ multiple types of field effect transistors having different threshold voltages, on-current per unit width, and off-current per unit length. Field effect transistors having a high threshold voltage are typically called “low power” devices, which have a low on-current and a low off-current. Field effect transistors having a low threshold voltage are called “high performance” devices, which has a high on-current and a high off-current. By employing a mixture of low power devices and high performance devices, a semiconductor chip may provide optimal performance at an optimal power consumption level.
Devices having different threshold voltages may be obtained by varying dopant concentration of a doped semiconductor well in which the body of a field effect transistor is formed for each value of the threshold voltages. Thus, a high performance device employs a doped semiconductor well having a low dopant concentration, while a low power device employs another doped semiconductor well having a high dopant concentration. Conventionally, for each setting of well doping, a dedicated implantation mask is employed during a corresponding ion implantation step for formation of a doped semiconductor well, which increases processing complexity and cost of manufacturing.
In addition to increased processing cost, low power devices employing a doped semiconductor well having a high dopant concentration also suffer from increased junction leakage. Typically, low power field effect transistors display a value of reverse junction leakage current over forward junction leakage current ratio that is many orders of magnitude higher than a corresponding value for high performance devices. Thus, low power field effect transistors require a high threshold voltage. Because complementary metal-oxide-semiconductor (CMOS) circuits employ both p-type field effect transistors and n-type field effect transistors, both p-type field effect transistors having a high threshold voltage and n-type field effect transistors having a high threshold voltage are necessary to provide low-power complementary metal-oxide-semiconductor (CMOS) circuits.
N-type field effect transistors having a high threshold voltage may be formed by employing a gate dielectric having a composite stack of a high dielectric constant (high-k) gate dielectric and an adjustment oxide layer. However, such a stack produces unacceptably low threshold voltages for p-type field effect transistors.
Selective removal of the adjustment oxide layer only from areas of p-type field effect transistors while maintaining the adjustment oxide in areas of n-type field effect transistors has been proposed to increase threshold voltages in p-type field effect transistors. Because the adjustment oxide layer is typically less than 1 nm thick, however, such selective removal of the adjustment oxide while maintaining uniformity of the underlying high-k gate dielectric layer has proven to be difficult for manufacturing purposes.